A conventional semiconductor integrated circuit will be described with reference to drawings.
FIG. 9A is a plan view of an ordinary construction of a semiconductor integrated circuit. FIG. 9B is a sectional view taken along line D-D′ in FIG. 9A. FIG. 9C is an enlarged view of portion E in FIG. 9B.
This conventional semiconductor integrated circuit has a five-layer wiring structure.
In the following description, a structure in which each of input/output signal electrode pads corresponding to those provided outside an element formation region for an input/output circuit in other structures is provided on an element formation region for an input/output circuit is referred to as a pad on element (POE) structure.
An ordinary construction in an electrode portion of the semiconductor integrated circuit having a five-layer wiring structure and a POE structure will be described briefly with reference to FIGS. 9A to 9C.
In FIGS. 9A to 9C, reference numeral 51 denotes the semiconductor integrated circuit (also called a semiconductor chip), reference numeral 52 an electrode pad having a POE structure; reference numeral 58 a first protective film of PSiN or the like; reference numeral 59 a second protective film of polyimide or the like; reference numeral 63 an interlayer insulating film; and reference numeral 65 a silicon substrate.
The electrode pad 52 having a POE structure has a stacked via structure formed by an uppermost-layer pad metal 60, a lower-layer pad metal 61 formed in a wiring layer immediately below the uppermost-layer pad metal 60, and a via 62 for connection between the two pad metals 60 and 61. This stacked via structure is effective in limiting cratering caused in a bonding step such as a wire bonding step.
A first power-supply-layer metal 68 for supplying power is formed below the electrode pad 52. A lowermost-layer metal 57 for supply of a signal to an input/output signal circuit is formed as a layer under the first power-supply-layer metal 68. The electrode pad 52 and the lowermost-layer metal 57 are electrically connected to each other by a stack structure of a lead metal 64.
A description based on the above description of the ordinary construction will be made of a semiconductor integrated circuit having a conventional electrode pad structure with reference to FIG. 10. FIG. 10 is an enlarged plan view corresponding to a portion F shown in FIG. 9A.
In the conventional semiconductor circuit having a POE structure, as shown in FIG. 10, a power supply electrode pad 54 is formed on a power supply cell 66, a GND electrode pad 55 is formed on a GND cell 67, and an input/output signal electrode pad 53 is formed on an element formation region of each of I/O cells 56 (an input/output circuit region).
Such a structure in which electrode pads are placed on element formation regions of cells for the purpose of reducing the chip size has already been proposed.
For example, a semiconductor integrated circuit has been proposed in which an interlayer insulating film is provided on a logic circuit or a driver circuit, and an electrode pad for an input signal or an output signal is formed on the interlayer insulating film (see, for example, Japanese Patent Laid-Open No. 6-244235).
In the above-described conventional semiconductor integrated circuit, however, the dependence of the chip size on the area of electrode pads tends to increase since the size of the active element region for the essential function of a semiconductor element is reduced with the adaptation of the diffusion process to finer design rules.
With the development of semiconductor integrated circuits operated at lower voltages, there is a tendency to increase the numbers of power supply pads and GND pads relative to the number of I/O cells for input and output signals for stabilization of signals for example. Because of the increase in the numbers of power supply pads and GND pads, the tendency of the dependence of the chip size on the area of electrode pads is further increased.
Conventionally, a reduction in electrode pad area in such semiconductor integrated circuits and, hence, a reduction in size of the semiconductor integrated circuits have been achieved by the method of reducing the size of electrode pads by reducing the pitch between the electrode pads.
There is a problem that, with the reduction in size of electrode pads by reducing the width of pads, assembly operations including operations to form wires and bumps on electrode pads and an operation to perform molding for resin encapsulation have become considerably difficult to perform.